As integrated circuit fabrication techniques become more sophisticated, feature sizes become increasingly smaller. According to typical techniques, manufacturing integrated circuits may require the use of several overlapping layers of masks that must be precisely positioned relative to each other to form desired structures. The positional accuracy of placement of the features on each integrated circuit mask may also be extremely important.
To make masks acceptable for use in manufacture of integrated circuits that meet state of the art standards, especially the positional accuracy requirements, some prior art systems utilize scanning electron beam pattern generators. Such state of the art devices typically employ interferometers to precisely position the workpiece supporting the photolithography mask blank and scan the workpiece with an electron beam in raster fashion. The electron beam is turned on and off to expose an electron sensitive photoresist layer over a layer of chromium so as to define the size, shape, and position of the features to be fabricated.
Such electron beam pattern generators are very expensive. Further, they must be employed in precisely controlled environments where temperature and humidity are controlled to very tight tolerances. Typically, temperature must be controlled to plus or minus 0.1.degree. C. Particulates in the air must also be eliminated or substantially reduced. Such operational environments are very expensive to build and maintain.
Integrated circuits, often referred to as chips or dies, are designed for many different purposes. The number of integrated circuits built depends upon the application of which the chip is designed. For example, in the case of a memory chip, millions may be built whereas an exotic microwave integrated circuit may have only a few hundred built. The microwave chip will, however, require the same or greater precision in feature size and positional accuracy as the memory chip. Since the cost to make a chip is related to the number made, it is apparent that making chips that require state of the art feature sizes and positional accuracy becomes impractical when a low volume of chips are to be made.
More generally, a large market exists for low volume, application specific integrated circuits (ASICs), many of which require state of the art circuit feature sizes and positional accuracy.
Typical integrated circuit processing systems may utilize 4x or 5x reticles or masks. This means that the feature sizes on the mask will be reduced in size by a factor of four or five during projection of the mask image on the die.
Although the use of 4x, 5x or other factor reduction lithography allows a somewhat relaxed tolerance for mask dimensions and feature placement, the mask is only allowed to contribute a small fraction of the total dimensional and positional error of the features printed on the semiconductor chip. As these tolerances decrease from year to year, it becomes increasingly difficult for electron beam pattern generated to meet the accuracy requirements placed on them.
U.S. Pat. No. 5,135,609, issued Aug. 4, 1992, to Pease et al., and assigned to The Board of Trustees of Leland Stanford Junior University, the entire disclosure of which is hereby incorporated by reference, provides one solution to the above-discussed problems. Pease et al. present what they refer to as a "quantum lithography mask" that includes a precisely created grid of lines separating tiles of mask material. Selected tiles may be removed to create a desired pattern in the mask to result in a desired pattern of exposure to a substrate. The tiles of masking material are processed so as to completely remove selected tiles, while leaving the remaining tiles with their edge intact. Thus, the dimensional and positional accuracy of the final pattern may be determined only by the accuracy of the tile and grid pattern generated on the mask substrate before the final patterning is performed.